View SNAD01B_352514.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

SNAD01B
8-CHANNEL 8-BIT ADC
========
1. 2. 3. 4. 5. 6.
CONTENTS
========
GENERAL DESCRIPTION.......................................................................................................................................3 FEATURES....................................................................................................................................................................3 APPLICATIONS ..........................................................................................................................................................3 BLOCK DIAGRAM.....................................................................................................................................................4 PIN ASSIGNMENT......................................................................................................................................................4 FUNCTIONAL DESCRIPTIONS .............................................................................................................................5 INTERFACE FORMAT.............................................................................................................................................................5 CHANNEL SETTING...............................................................................................................................................................7 CONTROL REGISTER SETTING..............................................................................................................................................7 ADC READ TIMING..............................................................................................................................................................8 TIMING OF DIGITAL INPUT READING...................................................................................................................................9 POWER DOWN & CHANNEL WAKE-UP.............................................................................................................................10 BANDGAP REFERENCE........................................................................................................................................................11 INPUT CHANNEL PAD (CHANNEL 0~6) ............................................................................................................................12 BATTERY MONITORING (CHANNEL 7 ONLY) ....................................................................................................................13
7. 8. 9.
ELECTRICAL CHARACTERISTICS ..................................................................................................................14 APPLICATION CIRCUITS .....................................................................................................................................15 EXAMPLE CIRCUIT: SNAD01B WORKS WITH SONIX 4-BIT SERIES CONTROLLER..........................................................15 EXAMPLE PROGRAMS:........................................................................................................................................16 PROGRAM 1: SET CONFIGURATION OF SNAD01B..........................................................................................................27 PROGRAM 2: READ ADC RESULT FROM CHANNEL 1 ......................................................................................................27 PROGRAM 3: READ DIGITAL INPUT DATA FROM CH4, CH3, CH2 ..................................................................................28 PROGRAM 4: POWER-DOWN SNAD01B AND HOST, AND WAKE-UP ..............................................................................28 PROGRAM 5: BATTERY LOW DETECTION .........................................................................................................................29
10.
PAD DIAGRAM...................................................................................................................................30
Version: 1.3
1
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
AMENDMENT HISTORY Version Date Ver 1.1 February 12, 2003 Ver 1.3 July 31, 2003 Description First issue. 1. Add the version code "B" of chip no. 2. This spec is modified form SNAD01_V1.3 3. Add standby current more than 50 uA in page 10
Note: This document is used to identify the different version "B" & "C" of SNAD01, the most important is standby current and power down setting between version "B" & "C". For the detail please refer to related section.
Version: 1.3
2
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
1. GENERAL DESCRIPTION
SNAD01B is a low cost serial 8-bits ADC with 8 individual input channels. Each channel can be independently programmed to a digital or analog input mode. In the analog input mode, this single-ended channel accepts an analog input signal from 0 to VREF and converts the signal into 12-bit digital codes (with 8-bit accuracy guaranteed). In the digital input mode, the channel can be treated as digital input port and the logic level appears at the channel can be acquired. SNAD01B has a synchronous 3-wires serial interface. Through this interface, the host CPU can easily control SNAD01B. During A-to-D conversion, the typical current consumption is 500uA at 25kHz throughput-rate and +3V power supply. SNAD01B includes a power-down mode, which reduces maximum current consumption to less than 1uA. The reference voltage can be varied between 1V and +VCC, providing a corresponding input voltage range of 0V to VREF. SNAD01B also has an on-chip 1.17V bandgap reference that can be utilized for constant voltage input (especially for battery monitoring applications). The bandgap reference circuitry consumes 300A@3v and can be enabled and disabled.
2. FEATURES
Single Supply: 2.7V ~ 5.25V Eight Analog/Digital Input Channels. Internal 1.17v Bandgap Reference for Battery Monitoring. (Channel 7) Low Power Consumption: typical operating current: 500uA @ 3V, Standby current <1uA. Up to 25kHz Conversion Rate. 8-bits Resolution with (8-bits) No Missing Code. 3-Wire Serial Interface.
3. APPLICATIONS
Battery-Powered Systems Instrumentation Portable Data Logging Test Equipment Data Acquisition Process-Control Monitoring
Version: 1.3
3
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Digital Input Bus Extender
4. BLOCK DIAGRAM
AVDD VDDD
1.2V Bandgap Reference
VRH CH0/DI0 CH1/DI1 CH2/DI2 CH3/DI3 CH4/DI4 CH5/DI5 CH6/DI6 CH7(BAT)/DI7
8-Channels Analog/Digital Input MUX
8-bit SAR ADC
Serial Interface and Control Logic
START CLK DIO
AVSS
VSSD
Figure1 Block diagram of ADC.
5. PIN ASSIGNMENT
Pin Name CH[7] ~ CH[0] REF VDD VSS AVDD AVSS START CLK DIO I/O I I I I I I I I IO Description Analog input / digital input Reference voltage of analog signal Positive power Negative power Positive power of analog circuit Negative power of analog circuit Command initialization signal (from host controller) Clock of data communication and AD conversion (from host controller) Data input and output of data communication
Version: 1.3
4
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
6. Functional Descriptions
VDD
Host CPU
Output Port1 Output Port2 I/O port START CLK DIO START CLK DIO
SNAD01
VDD AVDD REF 0.1uF VSS AVSS
CH[0] CH[1] Analog/Digital Signal
CH[7]
Figure2 Interface with Host CPU
Interface Format
START CLK Channel Setting HiZ DIO
CM2 CM1 CM0 CH[7] CH[6] CH[5] CH[4] CH[3] CH[2] CH[1] CH[0] Port Input PH PL RF MB xx xx xx Port Input xx D7 D6 D5 D4 Port Output D3 xx
xxx
Control Register Setting DIO HiZ CM2 CM1 CM0
xxx
ADC Reading HiZ DIO
CM2 CM1 CM0 ID2 ID1 ID0 Port Input Digital Input Reading HiZ DIO CM2 CM1 CM0 DI[7] DI[6] DI[5] Power Down HiZ DIO Port Input CM2 CM1 CM0 Port Input
D2
D1
D0
DI4]
DI[3] DI[2] DI[1] DI[0] DI[7] DI[6] DI[5] Port Output
DI4]
DI[3]
PDS Port Output
~PDS
Figure3 Timing Diagram of Whole Commands
Version: 1.3
5
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
1.DIO is HiZ while START is HIGH. 2.The interface logic begins to interpret a command at the falling edge of the START signal. 3.The command ID (sent by Host) is received in the first three clock cycles from DIO. 4. The operations include Channel setting, ADC Reading, Digital Input Reading and Power Down. 5.DIO becomes to HiZ while START returns to HIGH. Command ID 000 001 010 Operation Power Down (0) Channel Attribute Setting (1:Analog, 0:Digital) Channel Wakeup Function Setting (1:Enable, 0:Disable) 011 100 101 110 111 Control Register Setting ADC Conversion Digital Input Reading Reserved Power Down (1) Table1 Command Description Table
1. 000/111: ADC enters into power down after receiving this command. 2. 001: Set the attribute each channel to be an analog or a digital input with the sequence of channel 7 to 0. (1:Analog; 0:Digital) 3. 010: Set the wakeup function of each channel to be enabled or disabled with the sequence of channel 7 to 0. (1:Enable; 0:Disable) 4. 011: Setting the values of control registers. 5. 100: ADC starts to convert the analog signal of the selected channel after receiving this command. 6. 101: ADC starts to read the digital input of every channel with the sequence of channel 7 to 0. 7. 110: ADC enters into testing mode.
Version: 1.3
6
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Channel Setting
START CLK DIO HiZ 0/0 0/1 1/0 CH[7] CH[6] CH[5] CH[4] CH[3] CH[2] CH[1] CH[0] xxx Port Input
Figure3 The timing diagram of channel attribute/wakeup setting Command 001: channel attribute setting. Command 010: wakeup function setting. In attribute setting, "1" means analog and "0" means digital. In wakeup setting, "1" means enable and "0" means disable. After all of the channels are set, the DIO port remains input mode and all the following data are ignored.
Control Register Setting
START CLK DIO HiZ 0 1 1 PH PL RF Port Input MB xxx xxx xxx xxx xxx
Figure4 The timing diagram of control registers setting
1. Command ID: (011) 2. 4-bit data behind command ID are loaded into control registers with the sequence of PH, PL, RF and MB. 3. The function of each control registers are as Table2.
Version: 1.3
7
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Name PH PL RF MB
Function Set the pull-up resistor of the channel in digital input mode. 1:ON, 0:OFF. Set the pull-down resistor of the channel in digital input mode. 1:ON, 0:OFF. Set the Bandgap reference. 1:ON, 0:OFF. For testing chip only, always set MB=0 in system power-on initialization routine. Table2 The function table of control registers
Note: 1. The condition of both PH=1 and PL=1 is prohibited. 2. Pull-up and pull-down resistors are not activated while the corresponding channel is set as analog input mode.
ADC Read Timing
START CLK tACQ DIO HiZ 1 0 0 ID2 ID1 ID0 xx xx D7 D6 D5 D4 D3 D2 D1 D0 PDS
Port Input
Port Output
Figure5 The timing diagram of ADC reading
1.Command ID: (100) 2.3-bit channel number data behind command ID. 3.The analog signal of the selected channel is sampled to ADC. ADC refers the reference voltage and converts the sampled analog signal to digital domain by successiveapproximation method. 4.The 8-bit output data (result of conversion) of ADC is sent to DIO port from MSB and is triggered by CLK. The maximum clock frequency is 500kHz @ 2.7v. (Maximum conversion rate=25KHz)
Version: 1.3
8
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
5.After the 8-bits ADC data has been sent out, if the START is kept in LOW and CLK is kept in High/Low transition, then the data with uncertain value are kept appearing on DIO. These data can just be ignored.
Channel ID[2:0] 000 001 010 011 100 101 110 111
Selected Channel CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
Table3 Channel Selection Table.
Timing of Digital Input Reading
START CLK HiZ
DIO
1
0
1
DI[7] DI[6] DI[5]
DI4]
DI[3] DI[2] DI[1] DI[0] DI[7] DI[6] DI[5] Port Output
DI4]
DI[3] DI[2] DI[1] DI[0] DI[7]
Port Input
Figure6 The timing diagram of the digital input reading
1. Command ID: (101). 2. The digital data of each channel is sent to the DIO port with the sequence of channel 7 to 0. 3. After all of the channels are read, if the START is kept in LOW and CLK is kept in HIGH/LOW transition, the digital data of each channel is sent to the DIO port again with the sequence of channel 7 to 0 cyclically. 4. Pulling START to HIGH terminates this digital input reading.
Note: Once a channel is programmed as analog type, the corresponding data is "0" in digital input reading command.
Version: 1.3
9
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Power Down & Channel Wake-Up
START CLK DIO DIO 0 1 0 1 0 1 SNAD01 enters into power-down mode
Figure7 The timing diagram of power down command
START CLK CH n CH n DIO Wake-Up Host CPU DIO HiZ HiZ Wake-Up Procedure Ending
Figure8 The timing diagram of power down command
1. The power down command (000/111) is sent to SNAD01B in the first three cycles, and then SNAD01B enters into power down mode at the 5th clock cycle, consuming almost no current (less than 1uA). 2. After SNAD01B enters power down (mode 0: command 000), SNAD01B sends "0" out to DIO until a valid logic transition appears on any wakeup-enabled digital input channel. Once the transition occurs, SNAD01B toggles DIO to "1" to inform host controller. After receiving "1" from DIO, host controller should turn START back to "1" to inform SNAD01B that the power-down stage is over. Otherwise, SNAD01B keeps sending out "1" to DIO and does not recognize any other transitions on any channels.
Version: 1.3
10
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
3. After SNAD01B enters power down (mode 1: command 111), SNAD01B sends "1" out to DIO until a valid logic transition appears on any wakeup-enabled digital input channel. Once the transition occurs, SNAD01B toggles DIO to "0" to inform host controller. After receiving "0" from DIO, host controller should turn START back to "1" to inform SNAD01B that the power-down stage is over. Otherwise, SNAD01B keeps sending out "1" to DIO and does not recognize any other transitions any the channels. 4. The CLK may stop but START ought to remain at LOW level in the whole power down mode.
Note: 1. Wakeup function is only dedicated to the channel which is digital input type AND wakeup-enabled. 2. In SNAD01B version, the standby current will more than 50uA in AD conversion reference voltage use "REF" pin connected external voltage.
Bandgap reference
VDD
to reference high of the ADC
ON CHIP
OFF CHIP
REF 1.2v bandgap reference VSS
RF
RF+RF MB
PAD
Figure8 Circuit diagram of ADC bandgap reference selection If the internal bandgap reference is turned ON (RF=1), the reference voltage of ADC is supplied by output voltage of the internal bandgap reference circuit. This bandgap consumes about 300 A. The output voltage of bandgap reference is around 1.17V typically. Note: MB for chip test only. Always set MB=0 with command (011) in System Power-On Initialization Routine.
Version: 1.3
11
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Input Channel PAD (Channel 0~6)
VDD ENCH[x]: 1: Analog In / 0: Digital In
PH&ENCH[x]
Pull-high resistor ENCH[x]
CH[x] Pull-low resistor
to ADC
DI[x]
PL&ENCH[x]
VSS
ENCH[x]
Figure9 Circuit diagram of the Input Channel PAD
1. If a channel is programmed to analog input mode, then the corresponding internal signal, ENCH[x],=1. As in Figure9, pull-high and pull-low are disabled. And the path to digital input is blocked. All digital reading operation of this channel will get the result "0". 2. If a channel is programmed to digital input mode, then the corresponding internal signal, ENCH[x],=0. As in Figure9, the path to ADC is removed. 3. While in digital input mode, this input port can be configured to be floating, weak pull up, or pull down by setting the control register PH and PL as Figure9, where PH&PL=1 is forbidden. The weak pull resistance is about 500K@3v. 4. The default status (digital/analog, pull up/down) of the channels are not defined after power on, so initialization of each channel to define a correct state should be done. 5. Mode of each channel (ENCH[x]) can be set by command 001.
Version: 1.3
12
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Battery Monitoring (Channel 7 only)
VDD ENCH[7] PH&ENCH[x] DI[7]
CH[7]
30k
20k 10k
ENCH[7]
to ADC
PL&ENCH[x]
Battery VSS
VSS
VSS
Figure10 The circuit of the Input pad of Channel 7
1.While read ADC command is sent and channel 7 is selected, ADC can be used to monitor the battery voltage.
2.The circuit of battery voltage monitoring is shown in Battery Monitoring (Channel7 only)
3.The battery voltage is six times ADC measuring voltage. Thus, the measured result equals to 1/6*battery voltage. 4.While channel 7 is set to the analog input mode, an input resistor (60k) exists from CH[7] to VSS. To save unnecessary power consumption, CH[7] should be switch to digital input type when CH[7] is not measured.
Note: CH[7] is different from the other 7 channels. The input voltage is reduced to 1/6 before it is sent into ADC.
Version: 1.3
13
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
7. ELECTRICAL CHARACTERISTICS
Typical values apply for VDD=VREF=3.0 V, TAMB=25 C unless otherwise noted.
Symbol Parameter min typ max t Analog-to-Digital Converter VDD IDD Operating voltage Operating current 2.7 3.0 400 5.25 650 V A A kHz 0.5 -0.5 8 50 LSB LSB Bits dB Bits VDD=2.7~5.25V VDD=3.0V VDD=5.0V Excluding bandgap reference Uni Conditions
IPDN FSMP
Power Down Current Conversion Rate (Throughput Rate)
0.1 30 40
2
DNL INL NMC SINAD
Differential Nonlinearity Integral Nonlinearity No Missing Code Signal to Noise and Distortion
ENOB
Effective Number of Bits
8
Bandgap reference VBG Bandgap reference output voltage IBG Operating current of BGR Digital Interface Weak pull up/down resistance VIL VIH VOL VOH Input low voltage Input high voltage Output low voltage Output high voltage Output drive/sink current of DIO -0.3 VDD-0.7 0 VDD-0.5 3 k 0.8 VDD+0.3 0.4 VDD 500 V V V V mA VOP=VDD-0.5v/VSS+0.5v VDD=3V 400 1.14 1.17 1.20 V
A
Version: 1.3
14
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
8. APPLICATION CIRCUITS
Example Circuit: SNAD01B works with Sonix 4-bit Series Controller
CH[0], CH[1], CH[2]: Analog Input CH[6]: Digital Input CH[7]: Battery Voltage Detect REF=VDD+
VDD VDD
4-bit Voice chip
P22 P21 P20 VSS START CLK DIO
SNAD01
VDD AVDD REF 0.1uF VSS AVSS
SN300/500 SN65/66/67/68/6A
CH[0] CH[1] CH[2]
Analog Signal Analog Signal Analog Signal
CH[6] CH[7] VDD
Figure11 SNAD01B works with Sonix 4-bit Series Controller
Version: 1.3
15
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
9. Example Programs:
Host Controller: SNC500. Application circuit is identical to Figure11. P22: START. P21: CLK. P20: DIO. Macro Programs: (def.h)
p2State port_l port_h ad_out_l ad_out_h tmp tmp1 equ equ equ equ equ equ equ m0 m1 m2 m3 m4 m5 m6
;;******************************** @ON_START macro mov and mov mov endm ;;******************************** @OFF_START macro mov or mov mov endm ;;******************************** @CLOCK macro mov or mov mov and mov mov endm ;;******************************** @Send_0 macro mov and a a #1110b p2state ;;HOST SEND 0 DIO a p2 a a p2 a #0010b p2state a #1101b p2state a ;;SET CLK L H AND H L a p2 a #0100b p2state p2state a a ;;SET START=1 a a p2 #1011b p2state a ;;SET START=0
p2state a
p2state a
Version: 1.3
16
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
mov mov endm ;;******************************** @Send_1 macro mov or mov mov endm ;;******************************** @Send macro data; mov mov and or mov mov endm ;;******************************** @Read_DIO macro mov mov and endm ;;******************************** @P20_Out_Mode macro mov mov endm ;;******************************** @P20_In_Mode macro mov mov mov and mov mov endm a p2s a a p2 #0001b a #1110b p2state a ;;SWITCH P2.0 (DIO) TO INPUT MODE a p2s #0000b a ;;SWITCH ALL 4-BIT OF P2 TO OUTPUT MODE a tmp a p2 #0001b tmp ;;READ DIO A.0 (1-BIT) a p2 tmp a a data #1110b p2state tmp p2state a a ;HOST SEND 1-BIT CONSTANT (#1 OR #0) DIO a p2 a #0001b p2state p2state a a ;;HOST SEND 1 DIO p2state a p2 a
p2state a
Version: 1.3
17
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
;;************************************************************************** ;; Set Analog/Digital Mode to each channel (1:Analog, 0:Digital) * ;; y7 Ch7. y6 Ch6. y5 Ch5, ... * ;;************************************************************************** @Set_Attrib macro y7,y6,y5,y4,y3,y2,y1,y0 @P20_Out_mode @ON_START @Send_0 @Clock @Send_0 @Clock @Send_1 @Clock @Send y7 @Clock @Send y6 @Clock @Send y5 @Clock @Send y4 @Clock @Send y3 @Clock @Send y2 @Clock @Send y1 @Clock @Send y0 @Clock @OFF_START ;; SET START=1 @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE endm ;;************************************************************************* ;; Set Wakeup function Enable/Disable (1:Enable, 0:Disable) ;; y7 Ch7. y6 Ch6. y5 Ch5, ... * * ;; SEND y7 TO y0 ;; SWITCH P2 TO OUTPUT MODE ;; SET START=0 ;; SEND COMMAND (001)
;;************************************************************************* @Set_Wakeup macro y7,y6,y5,y4,y3,y2,y1,y0 @P20_Out_mode ;; SWITCH P2 TO OUTPUT MODE
Version: 1.3
18
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
@ON_START @Send_0 @Clock @Send_1 @Clock @Send_0 @Clock @Send y7 @Clock @Send y6 @Clock @Send y5 @Clock @Send y4 @Clock @Send y3 @Clock @Send y2 @Clock @Send y1 @Clock @Send y0 @Clock @OFF_START endm
;; SET START=0 ;; SEND COMMAND (010)
;; SEND y7 TO y0
;; SET START=1
@P20_In_mode ;; SWITCH P2.0 TO INPUT MODE ;;********************************************************************** ;; Setup Control Register ;; ph: PULL-HIGH register. pl:PULL-LOW register. ;; rf: BANDGAP reference enable ;; mb: Set 0 always @Set_Control_Reg macro ph,pl,rf,mb @P20_Out_mode @ON_START @Send_0 @Clock @Send_1 ;; SWITCH P2 TO OUTPUT MODE ;; SET START=0 ;; SEND COMMAND (011) * * * *
;;**********************************************************************
Version: 1.3
19
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
@Clock @Send_1 @Clock @Send ph @Clock @Send pl @Clock @Send rf @Clock @Send mb @Clock @OFF_START ;; SET START=1 @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE endm ;;******************************************************************* ;; Let SNAD01B Enter Power-Down mode 0 @Power_Down_0 macro @P20_Out_mode @ON_START @Send_0 @Clock @Send_0 @Clock @Send_0 @Clock @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE @Clock @Clock @Clock @Clock @Clock Endm ;; SNAD01B ENTERS POWER-DOWN AT THE 8-th CLOCK EDGE. ;; SWITCH P2 TO OUTPUT MODE ;; SET START=0 ;; SEND COMMAND (000) * ;;******************************************************************* ;; SEND ph, pl, rf, mb
Version: 1.3
20
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
;;***************************************************************** ;; Let SNAD01B Enter Power-Down mode 1 @Power_Down_1 macro @P20_Out_mode @ON_START @Send_1 @Clock @Send_1 @Clock @Send_1 @Clock @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE @Clock @Clock @Clock @Clock @Clock endm ;;***************************************************************** ;; Read ADC from Channel n (n=n2,n1,n0) ;; e.g.: Ch 5 (n2, n1, n0= #1, #0, #1 ;; 8-bit Data @Read_ADC (ad_out_h, ad_out_l) macro n0, n1, n2 ;; SWITCH P2 TO OUTPUT MODE ;; SET START=0 ;; SEND COMMAND (100) * * * ;; SNAD01B ENTERS POWER-DOWN AT THE 8-th CLOCK EDGE. ;; SWITCH P2 TO OUTPUT MODE ;; SET START=0 ;; SEND COMMAND (111) * ;;*****************************************************************
;;***************************************************************** @P20_Out_mode @ON_START @Send_1 @Clock @Send_0 @Clock @Send_0 @Clock @Send n2 @Clock @Send n1 @Clock ;; SEND CHANNEL NUMBER
Version: 1.3
21
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
@Send n0 @Clock @p20_in_mode ;; SWITCH P2.0 TO INPUT MODE @Clock @Clock mov ad_out_l #0 mov ad_out_h #0 ;;*************************************** @Clock mov tmp1 #1000b @f ad_out_h tmp1 ad_out_h a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0100b @f ad_out_h tmp1 ad_out_h a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0010b @f ad_out_h tmp1 ad_out_h a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0001b @f @Read_DIO caje #0 ;; READ DIO and SAVE 1-bit DATA in ad_out_h.0 a a ;; READ DIO and SAVE 1-bit DATA in ad_out_h.1 a a ;; READ DIO and SAVE 1-bit DATA in ad_out_h.2 a a ;; READ DIO and SAVE 1-bit DATA in ad_out_h.3 ;; WAIT FOR 2 MORE CLOCKS
Version: 1.3
22
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
mov or mov @@: a
a
ad_out_h tmp1
ad_out_h a
;;*************************************** @Clock mov tmp1 #1000b @f ad_out_l tmp1 ad_out_l a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0100b @f ad_out_l tmp1 ad_out_l a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0010b @f ad_out_l tmp1 ad_out_l a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0001b @f ad_out_l tmp1 ad_out_l a @Read_DIO caje #0 mov or mov @@: ;;*************************************** a a ;; READ DIO and SAVE 1-bit DATA in ad_out_l.0 a a ;; READ DIO and SAVE 1-bit DATA in ad_out_l.1 a a ;; READ DIO and SAVE 1-bit DATA in ad_out_l.2 a a ;; READ DIO and SAVE 1-bit DATA in ad_out_l.3
Version: 1.3
23
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
@Clock @OFF_START endm ;;***************************************************************** ;; Read Digital Input: ;; 8-bit Data @Read_Port (port_h, port_l) macro ;; SWITCH P2 TO OUTPUT MODE ;; SET START=0 ;; SET COMMAND (101) * * ;; SET START=1
;;***************************************************************** @P20_Out_mode @ON_START @Send_1 @Clock @Send_0 @Clock @Send_1 @Clock @P20_In_mode ;; SWITCH P2.0 TO INPUT MODE mov mov port_l #0 port_h #0 ;; READ DIO and SAVE 1-bit DATA in port_h.3 #1000b
;;*************************************** @Clock mov tmp1 @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0100b @f port_h tmp1 a @Read_DIO caje #0 mov or mov a a port_h ;; READ DIO and SAVE 1-bit DATA in port_h.2 a a port_h @f port_h tmp1 a
Version: 1.3
24
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
@@: ;;*************************************** @Clock mov tmp1 #0010b @f port_h tmp1 a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0001b @f port_h tmp1 a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #1000b @f port_l tmp1 a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0100b @f port_l tmp1 a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock mov tmp1 #0010b @Read_DIO ;; READ DIO and SAVE 1-bit DATA in port_l.1 a a port_l ;; READ DIO and SAVE 1-bit DATA in port_l.2 a a port_l ;; READ DIO and SAVE 1-bit DATA in port_l.3 a a port_h ;; READ DIO and SAVE 1-bit DATA in port_h.0 a a port_h ;; READ DIO and SAVE 1-bit DATA in port_h.1
Version: 1.3
25
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
caje #0 mov or mov @@: a a port_l
@f port_l tmp1 a
;;*************************************** @Clock mov tmp1 #0001b @f port_l tmp1 a @Read_DIO caje #0 mov or mov @@: ;;*************************************** @Clock @OFF_START endm ;;*************************************** ;; SET START=1 a a port_l ;; READ DIO and SAVE 1-bit DATA in port_l.0
Version: 1.3
26
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Program 1: Set Configuration of SNAD01B
;; Setup Configuration of SNAD01B ;; ;; With Pull-Low, Bandgap ON. (PH=0, PL=1, RF=0,MB=0) ;; ;; CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 ;; Analog/Digital: B A A D D D A A :B, battery detect ;; Wakeup: X X X NO YES YES X X ;;
SNC520 program include def.h START: mov mov mov mov mov
a #1111b p2s a a #0000b p2 a p2State #0 ;; Set Control Registers ;; Set Chan Analog/Digital ;; Setup Wakeup function
@Set_Control_Reg #0, #1, #0, #0 @Set_Attrib #0, #1, #1, #0, #0, #0, #1, #1 @Set_Wakeup #0, #0, #0, #0, #1, #1, #0, #0
Program 2: Read ADC result from Channel 1
;; Inherit from program 1 ;; 8-bit ADC result of channel 1 in ( ad_out_h, ad_out_l) @Read_ADC #0, #0, #1 ;;get ADC result from Ch1 in ( ad_out_h, ad_out_l)
... ...
Version: 1.3
27
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Program 3: Read Digital Input data from Ch4, Ch3, CH2
;; Inherit from program 1 ;; After Reading, ;; Port_h.0 = Input of Ch4 ;; Port_l.3 = Input of Ch3 ;; Port_l.2 = Input of Ch2 @Read_Port ... ... ;;get ADC result in ( ad_out_h, ad_out_l)
Program 4: Power-down SNAD01B and Host, and Wake-up
;; Inherit from program 1 ;; Enter Power-down Mode (0) @Power_Down_0 end ... ... TRIGGER: @OFF_START ... @Read_Port ... ... ;;SNAD01B enters power-down Mode (0) ;; HOST (SNC520) enter power-down
;; SET START=1 ;; READ Trigger condition or Debounce Procedure starting from here
Version: 1.3
28
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Program 5: Battery Low Detection
VDD VDD SNC520 VDD P22 P21 P20 VSS START CLK DIO SNAD01B VDD AVDD REF 0.1uF VSS AVSS CH[7] VDD VDD
Battery: 1.5Vx3
An application uses three 1.5V batteries for power supply. During operation, the power of batteries keeps consumed and the voltage of battery keeps going down. Now, voltage lower than 3.6V is treated as "Battery Low". The ADC and bandgap reference circuit in SNAD01B can be utilized to detect "Battery Low". The voltage through channel 7 to ADC is reduced to 1/6*VDD (Figure10). Thus, when VDD=3.6V, the voltage into ADC is around 0.6V. And bandgap is chosen for reference voltage (approximately 1.17V within the whole operation voltage range). The value acquired from ADC is about (0.6/1.17)*256=131. For simplification consideration, we choose "ADC's readout < 128" as "Battery Low" condition.
;; Inherit from program 1 ;; Enter Power-down Mode (0) CheckBattery: @Set_Control_Reg #0, #1, #1, #0 ;; Set rf=1, turn-on bandgap @Set_Attrib #1, #1, #1, #0, #0, #0, #1, #1 ;; Switch Ch7 to Analog mov m15 #0 CheckAgain: @Read_ADC #1, #1, #1 mov a #1000b and a ad_out_h caje #1000b Battery_Low_No mov a m15 inca mov m15 a caje #3 Battery_Low_Yes jmp CheckAgain Battery_Low_Yes: mov m14 #1 Version: 1.3
;; Read Ch7
;; if (Value>=128) then Not Battery Low
;; if (Value<128) for 3 times, then ;; battery low.
29
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
Battery_Low_No: @Set_Control_Reg #0, #1, #0, #0 ;; Set rf=0, turn-off bandgap @Set_Attrib #0, #1, #1, #0, #0, #0, #1, #1 ;; Switch Ch7 to Digital ;; To save operating current
10. PAD DIAGRAM
Dice Form
NO 1 2 3 4 5 6 7 8 PAD NAME CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 X(um) -623.50 -623.50 -623.50 -623.50 -623.50 -623.50 -623.50 -623.50 Y(um) 352.50 242.50 132.50 22.50 -87.50 -197.50 -307.50 -417.50 NO 9 10 11 12 13 14 15 16 PAD NAME VSS VDD DIO CLK START AVDD VSS REF X(um) 623.50 623.50 623.50 623.50 623.50 623.50 623.50 623.50 Y(um) -417.50 -307.50 -197.50 -87.50 22.50 132.50 242.50 352.50
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7
1 2 3 4 5 6 7 8
(0,0)
16 15 14 13 12 11 10 9
REF AVSS AVDD START CLK DIO VDD VSS
CHIP SIZE=1350 x 950um
SNAD01B
Note: The substrate MUST be connected to Vss in PCB layout
Version: 1.3
30
July 31, 2003
SNAD01B
8-CHANNEL 8-BIT ADC
DISCLAIMER The information appearing in SONiX web pages ("this publication") is believed to be accurate. However, this publication could contain technical inaccuracies or typographical errors. The reader should not assume that this publication is error-free or that it will be suitable for any particular purpose. SONiX makes no warranty, express, statutory implied or by description in this publication or other documents which are referenced by or linked to this publication. In no event shall SONiX be liable for any special, incidental, indirect or consequential damages of any kind, or any damages whatsoever, including, without limitation, those resulting from loss of use, data or profits, whether or not advised of the possibility of damage, and on any theory of liability, arising out of or in connection with the use or performance of this publication or other documents which are referenced by or linked to this publication. This publication was developed for products offered in Taiwan. SONiX may not offer the products discussed in this document in other countries. Information is subject to change without notice. Please contact SONiX or its local representative for information on offerings available. Integrated circuits sold by SONiX are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. The application circuits illustrated in this document are for reference purposes only. SONIX DISCLAIMS ALL WARRANTIES, INCLUDING THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. SONIX reserves the right to halt production or alter the specifications and prices, and discontinue marketing the Products listed at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. Products described herein are intended for use in normal commercial applications. Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SONIX for such application.
Version: 1.3
31
July 31, 2003

▲Up To Search▲

Price & Availability of SNAD01B

	To Download SNAD01B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .